Stitching IC Images

Piché, Robert and Keyes, Edward (2002) Stitching IC Images. Canadian Industrial Problem Solving Workshops > 6th IPSW [Vancouver 27/5/2002 - 31/5/2002].

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Abstract/Summary

Image stitching software is used in many areas such as photogrammetry, biomedical imaging, and even amateur digital photography. However, these algorithms require relatively large image overlap, and for this reason they cannot be used to stitch the integrated circuit (IC) images, whose overlap is typically less than 60 pixels for a 4096 by 4096 pixel image.

In this paper, we begin by using algorithmic graph theory to study optimal patterns for adding IC images one at a time to a grid. In the remaining sections we study ways of stitching all the images simultaneously using different optimisation approaches: least squares methods, simulated annealing, and nonlinear programming.

Item Type:	Study Group Report
Study Group:	Canadian Industrial Problem Solving Workshops > 6th IPSW [Vancouver 27/5/2002 - 31/5/2002]
Company Name:	Semiconductor Insights
Industrial Sector:	None/Other Information and communication technology
Additional Contributors:	Baumann, Michael and Bose, Chris and Dame, Lorraine and Dechene, Isabelle and Goncalves, Maria Inez and Israel, Robert and Lutscher, Frithjof and Lyder, David and Macdonald, Colin and McNulty, Jenny and Morris, Joy and Neudauer, Nancy Ann and Ong, Benjamin and Aruna, Šalkauskas and Seyffarth, Karen and Stevens, Brett and Vassilev, Tzvetalin and Wetton, Brian and Youbissi, Fabien
ID Code:	173
Deposited By:	Michele Taroni
Deposited On:	13 October 2008

Problem Statement

Errors in stitching (or mosaicing) of integrated circuit (IC) images cause errors in the automated generation of the schematic. This increases costs and introduces delays as engineers must step in with interactive computer tools to correct the stitching. Our goal was to develop automated image stitching methods that keep stitching errors under F/2, where the minimum feature size F is around 10 pixels.

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